commit 930e1249070dd553a790000662cc488ff6d7572d Author: Uwe Klotz <uwe.klotz(a)gmail.com&gt; Date: Mon Apr 17 22:45:24 2023 +0200 Add aarch64_asm_operand_widths.patch aarch64_asm_operand_widths.patch | 51 ++++++++++++++++++++++++++++++++++++++++ mixxx.spec | 1 + 2 files changed, 52 insertions(+) --- diff --git a/aarch64_asm_operand_widths.patch b/aarch64_asm_operand_widths.patch new file mode 100644 index 0000000..96aa547 --- /dev/null +++ b/aarch64_asm_operand_widths.patch @@ -0,0 +1,51 @@ +From 2652d52d26125b589c36e1b5251ff39bd872ce45 Mon Sep 17 00:00:00 2001 +From: Uwe Klotz <uwe.klotz(a)gmail.com&gt; +Date: Mon, 17 Apr 2023 22:41:32 +0200 +Subject: [PATCH] aarch64: Fix -Wasm-operand-widths + +--- + src/soundio/sounddevicenetwork.cpp | 4 ++-- + src/soundio/sounddeviceportaudio.cpp | 4 ++-- + 2 files changed, 4 insertions(+), 4 deletions(-) + +diff --git a/src/soundio/sounddevicenetwork.cpp b/src/soundio/sounddevicenetwork.cpp +index aff65b9dc0..06db529f5b 100644 +--- a/src/soundio/sounddevicenetwork.cpp ++++ b/src/soundio/sounddevicenetwork.cpp +@@ -462,12 +462,12 @@ void SoundDeviceNetwork::callbackProcessClkRef() { + // Flush-to-zero on aarch64 is controlled by the Floating-point Control Register + // Load the register into our variable. + int savedFPCR; +- asm volatile("mrs %[savedFPCR], FPCR" ++ asm volatile("mrs %w[savedFPCR], FPCR" + : [ savedFPCR ] "=r"(savedFPCR)); + + qDebug() << "aarch64 FPCR: setting bit 24 to 1 to enable Flush-to-zero"; + // Bit 24 is the flush-to-zero mode control bit. Setting it to 1 flushes denormals to 0. +- asm volatile("msr FPCR, %[src]" ++ asm volatile("msr FPCR, %w[src]" + : + : [ src ] "r"(savedFPCR | (1 << 24))); + #endif +diff --git a/src/soundio/sounddeviceportaudio.cpp b/src/soundio/sounddeviceportaudio.cpp +index 681d0942cc..b36578147c 100644 +--- a/src/soundio/sounddeviceportaudio.cpp ++++ b/src/soundio/sounddeviceportaudio.cpp +@@ -936,12 +936,12 @@ int SoundDevicePortAudio::callbackProcessClkRef( + // Flush-to-zero on aarch64 is controlled by the Floating-point Control Register + // Load the register into our variable. + int savedFPCR; +- asm volatile("mrs %[savedFPCR], FPCR" ++ asm volatile("mrs %w[savedFPCR], FPCR" + : [ savedFPCR ] "=r"(savedFPCR)); + + qDebug() << "aarch64 FPCR: setting bit 24 to 1 to enable Flush-to-zero"; + // Bit 24 is the flush-to-zero mode control bit. Setting it to 1 flushes denormals to 0. +- asm volatile("msr FPCR, %[src]" ++ asm volatile("msr FPCR, %w[src]" + : + : [ src ] "r"(savedFPCR | (1 << 24))); + #endif +-- +2.40.0 + diff --git a/mixxx.spec b/mixxx.spec index 7d7582b..2702f99 100644 --- a/mixxx.spec +++ b/mixxx.spec @@ -34,6 +34,7 @@ Source0: https://github.com/mixxxdj/%{name}/archive/%{sources}/%{name}-%{ # as a fragment identifier to the URL to populate SOURCE1 correctly Source1: https://github.com/mixxxdj/libkeyfinder/archive/refs/tags/v%{libkeyfinder... Patch0: disable_werror_in_tests.patch +Patch1: aarch64_asm_operand_widths.patch # TODO: Switch back from "clang" to "gcc" after issues have been fixed? # See also: <https://github.com/mixxxdj/mixxx/issues/11483>