commit 31c6eb1a68572d4d0f1a38d554c842893b04be98 Author: Leigh Scott <leigh123linux(a)gmail.com&gt; Date: Wed Mar 16 07:20:20 2022 +0000 Update to 99.0.4844.74 chromium-freeworld.spec | 7 ++-- chromium-gcc-12-subzero-fix.patch | 69 +++++++++++++++++++++++++++++++++++++++ sources | 2 +- 3 files changed, 75 insertions(+), 3 deletions(-) --- diff --git a/chromium-freeworld.spec b/chromium-freeworld.spec index a9debb8..6305d62 100644 --- a/chromium-freeworld.spec +++ b/chromium-freeworld.spec @@ -42,8 +42,8 @@ ##############################Package Definitions###################################### Name: chromium-freeworld -Version: 99.0.4844.51 -Release: 2%{?dist} +Version: 99.0.4844.74 +Release: 1%{?dist} Summary: Chromium built with all freeworld codecs and VA-API support License: BSD and LGPLv2+ and ASL 2.0 and IJG and MIT and GPLv2+ and ISC and OpenSSL and (MPLv1.1 or GPLv2 or LGPLv2) URL: https://www.chromium.org/Home @@ -565,6 +565,9 @@ appstream-util validate-relax --nonet "%{buildroot}%{_metainfodir}/%{name}.appda %{chromiumdir}/vk_swiftshader_icd.json #########################################changelogs################################################# %changelog +* Tue Mar 15 2022 Leigh Scott <leigh123linux(a)gmail.com&gt; - 99.0.4844.74-1 +- Update to 99.0.4844.74 + * Mon Mar 14 2022 Leigh Scott <leigh123linux(a)gmail.com&gt; - 99.0.4844.51-2 - Test spec file changes diff --git a/chromium-gcc-12-subzero-fix.patch b/chromium-gcc-12-subzero-fix.patch new file mode 100644 index 0000000..fd5bbdb --- /dev/null +++ b/chromium-gcc-12-subzero-fix.patch @@ -0,0 +1,69 @@ +diff -up chromium-98.0.4758.102/third_party/swiftshader/third_party/subzero/src/IceInstX8664.cpp.gcc12fix chromium-98.0.4758.102/third_party/swiftshader/third_party/subzero/src/IceInstX8664.cpp +--- chromium-98.0.4758.102/third_party/swiftshader/third_party/subzero/src/IceInstX8664.cpp.gcc12fix 2022-02-25 22:17:18.071775686 +0000 ++++ chromium-98.0.4758.102/third_party/swiftshader/third_party/subzero/src/IceInstX8664.cpp 2022-02-25 22:17:40.964996468 +0000 +@@ -659,6 +659,7 @@ void emitIASOpTyGPR(const Cfg *Func, Typ + } + } + ++#if 0 + template <bool VarCanBeByte, bool SrcCanBeByte> + void emitIASRegOpTyGPR(const Cfg *Func, Type Ty, const Variable *Var, + const Operand *Src, const GPREmitterRegOp &Emitter) { +@@ -697,6 +698,7 @@ void emitIASRegOpTyGPR(const Cfg *Func, + llvm_unreachable("Unexpected operand type"); + } + } ++#endif + + void emitIASAddrOpTyGPR(const Cfg *Func, Type Ty, const AsmAddress &Addr, + const Operand *Src, const GPREmitterAddrOp &Emitter) { +diff -up chromium-98.0.4758.102/third_party/swiftshader/third_party/subzero/src/IceInstX8664.h.gcc12fix chromium-98.0.4758.102/third_party/swiftshader/third_party/subzero/src/IceInstX8664.h +--- chromium-98.0.4758.102/third_party/swiftshader/third_party/subzero/src/IceInstX8664.h.gcc12fix 2022-02-25 22:17:51.409640955 +0000 ++++ chromium-98.0.4758.102/third_party/swiftshader/third_party/subzero/src/IceInstX8664.h 2022-02-25 22:19:13.478847553 +0000 +@@ -576,8 +576,44 @@ void emitIASXmmShift(const Cfg *Func, Ty + /// Emit a two-operand (GPR) instruction, where the dest operand is a Variable + /// that's guaranteed to be a register. + template <bool VarCanBeByte = true, bool SrcCanBeByte = true> +-void emitIASRegOpTyGPR(const Cfg *Func, Type Ty, const Variable *Dst, +- const Operand *Src, const GPREmitterRegOp &Emitter); ++ ++void emitIASRegOpTyGPR(const Cfg *Func, Type Ty, const Variable *Var, ++ const Operand *Src, const GPREmitterRegOp &Emitter) { ++ auto *Target = InstX86Base::getTarget(Func); ++ Assembler *Asm = Func->getAssembler<Assembler>(); ++ assert(Var->hasReg()); ++ // We cheat a little and use GPRRegister even for byte operations. ++ GPRRegister VarReg = VarCanBeByte ? RegX8664::getEncodedGPR(Var->getRegNum()) ++ : RegX8664::getEncodedGPR(Var->getRegNum()); ++ if (const auto *SrcVar = llvm::dyn_cast<Variable>(Src)) { ++ if (SrcVar->hasReg()) { ++ GPRRegister SrcReg = SrcCanBeByte ++ ? RegX8664::getEncodedGPR(SrcVar->getRegNum()) ++ : RegX8664::getEncodedGPR(SrcVar->getRegNum()); ++ (Asm->*(Emitter.GPRGPR))(Ty, VarReg, SrcReg); ++ } else { ++ AsmAddress SrcStackAddr = AsmAddress(SrcVar, Target); ++ (Asm->*(Emitter.GPRAddr))(Ty, VarReg, SrcStackAddr); ++ } ++ } else if (const auto *Mem = llvm::dyn_cast<X86OperandMem>(Src)) { ++ Mem->emitSegmentOverride(Asm); ++ (Asm->*(Emitter.GPRAddr))(Ty, VarReg, AsmAddress(Mem, Asm, Target)); ++ } else if (const auto *Imm = llvm::dyn_cast<ConstantInteger32>(Src)) { ++ (Asm->*(Emitter.GPRImm))(Ty, VarReg, AssemblerImmediate(Imm->getValue())); ++ } else if (const auto *Imm = llvm::dyn_cast<ConstantInteger64>(Src)) { ++ assert(Utils::IsInt(32, Imm->getValue())); ++ (Asm->*(Emitter.GPRImm))(Ty, VarReg, AssemblerImmediate(Imm->getValue())); ++ } else if (const auto *Reloc = llvm::dyn_cast<ConstantRelocatable>(Src)) { ++ const auto FixupKind = (Reloc->getName().hasStdString() && ++ Reloc->getName().toString() == GlobalOffsetTable) ++ ? FK_GotPC ++ : FK_Abs; ++ AssemblerFixup *Fixup = Asm->createFixup(FixupKind, Reloc); ++ (Asm->*(Emitter.GPRImm))(Ty, VarReg, AssemblerImmediate(Fixup)); ++ } else { ++ llvm_unreachable("Unexpected operand type"); ++ } ++} + + /// Instructions of the form x := op(x). + template <typename InstX86Base::InstKindX86 K> diff --git a/sources b/sources index 1ba090c..34faf69 100644 --- a/sources +++ b/sources @@ -1,2 +1,2 @@ -SHA512 (chromium-99.0.4844.51.tar.xz) = 85f81afa35907d59e7dee328c1c30d61a4106b8d5e9dabad4888c0a1962d8e4debfb88358417123979d8a4ad471acbf8d90c0a3bb2cc9bac5fef71b800bcc1af +SHA512 (chromium-99.0.4844.74.tar.xz) = d0b8d8fff715b249bbc214d30d7165ecd75f399c3a5d5234e7b8492bdfa2c0a1f24ed25ea33efe43f0c1210fa5ec65566be7eba7817e5566f1e0cdcae92214de SHA512 (chromium-patches-chromium-99-patchset-3.tar.gz) = 8dcd3acb256f32b1af0c0ef3eea61061c1d857f8887f2990ec170bc87a3f49a9a8b15dfe50ac05e3eedabea33e88365f91094550237b5500ffa7f66734523b76